ATA8742-PXQW【PDF 68/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

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9151AINDCO07/09

ATA8742

18. External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as

outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts

PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1 will trigger if

any enabled PCINT11..8 pin toggles. The PCMSK0 and PCMSK1 Registers control which pins

contribute to the pin change interrupts. Pin change interrupts on PCINT11..0 are detected asyn-

chronously. This implies that these interrupts can be used for waking the part also from sleep

modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the MCU Control Register MCUCR. When the INT0 interrupt is

enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held

low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an

I/O clock, described in Clock Systems and their Distribution on page 41. Low level interrupt on

INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part

also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except

Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in System Clock and Clock Options on page 41.

18.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure .

Timing of pin change interrupts

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF

PCINT(0)

pin_sync

pcint_syn

pin_lat

D Q

pcint_setflag

PCIF

clk

PCINT(0) in PCMSK(x)

pcint_in_(0)

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